SystemVerilog for Hardware Description: RTL Design and Verification

Logic Design and Verification Using SystemVerilog (Revised)

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using ASIC FPGA Design

The VLSI Verification Interview Handbook: SystemVerilog, UVM, AMBA and Modern SoC Design

CIRCUITON Digital System MODELING: Hardware Abstraction Techniques for Simulation Verification and Synthesis...