Destacado
Comparar tiendas web (1)
Páginas: 276, Edición: 1st edition 2020, Tapa blanda, Springer
CREATESPACE
Logic Design and Verification Using SystemVerilog (Revised)
RTL Modeling with SystemVerilog for Simulation and Synthesis: Using ASIC FPGA Design
Independently Published
The VLSI Verification Interview Handbook: SystemVerilog, UVM, AMBA and Modern SoC Design
Newnes
Co-verification of Hardware and Software for ARM SoC Design
Volver arriba